View EM83040B_450499.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM83040B LCD CONTROLLER
ar y relimin P
GENERAL DESCRIPTION
The EM83040B is a dot matrix LCD driver, which is fabricated by low power CMOS technology. This chip includes 80-bits shift register, 80 bits data latch and 80 bits level driver. A LCD RAM inside can be mapping to LCD signal. It converts RAM data to parallel data and output waveform to LCD.
FEATURES
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Supply power: 2.5~5.5V LCD drive voltage: 3.6 to15V Internal RAM: 2.5k x 4 bits RAM can be controlled by eight signals including four bits data bus. Duty: 1/32, 1/48, 1/64, 1/80 Build in DC/DC converter: double, triple, quad and five times. Modularized function: connect to another 83040B to extent LCD matrix One DC converter enabled and other 83040B can share with this. Internal regulator output for DC/DC converter controlled by control register. Chip form (EM83040BH), 128 pin package (14mm x 20mm EM83040BAQ), 160 pin package (EM83040BBQ) (11) Bias: 1/5 (32 COMMON), 1/7 (48 COMMON), 1/9 (64 and 80 COMMON) fixed by internal circuit. (12) Internal RC clock about 250 KHz.
APPLICATION
(1) (2) (3) Data Bank LCD toy Education computer
* This specification are subject to be changed without notice.
9.14.2001
1
EM83040B LCD CONTROLLER
ary relimin P
PIN ASSIGNMENTS
EM83040BAQ
MAIN M1 M0 EN NC NC NC NC RAMEN RAMADS RAMW RAMR RAMD3 RAMD2 RMAD1 RAMD0 LOAD VDD GND VOUT VSS4 VSS3 CB CA VSS2+ VSS2V1 V2 VREG NC NC NC NC NC V3 V4 V5 O0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
EM83040BAQ
O53 O52 O51 NC NC NC NC NC O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 NC NC NC NC NC NC O29 O28 O27
* This specification are subject to be changed without notice.
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
9.14.2001
2
EM83040B LCD CONTROLLER
ar y relimin P
EM83040BBQ
VOUT VSS4 VSS3 + -
EM83040BBQ
VREG
* This specification are subject to be changed without notice.
9.14.2001
3
EM83040B LCD CONTROLLER
BLOCK DIAGRAM
ary relimin P
VOUT VSS4 VSS3 CA CB VSS2+ VSS2-
REG(5~0)
Regulator
VREG
M1,M0 IR(2~0)
Resistance ratio
V1 Buffer1 Buffer2 Buffer3 Buffer4 Buffer5
MUX
:::::
BIAS
* This specification are subject to be changed without notice.
9.14.2001
4
EM83040B LCD CONTROLLER
PIN DESCRIPTIONS
Symbol VDD GND VOUT I/O Power Power Power
ar y relimin P
Function System power supply Ground Voltage converter input/output pin Connect this pin to GND through capacitor EN=1,VOUT=VDD Step-up capacitor EN=1, VSS4=VDD Step-up capacitor EN=1, VSS3=VDD Step-up capacitor EN=1, VSS2=VDD Step-up capacitor Output voltage regulator terminal. Provides the voltage between V1 and GND through a resistive voltage divider. Master or slave control signal. MAIN=1, master unit MAIN=0, slave unit This pin control whole chip power. This chip will work when this pin is connected to ground. And whole chip will disable when connect to VDD voltage. EN=0 and MAIN=1 the chip will generate VSS2+, VSS2VSS3, VSS4, VOUT, LOAD signal and internal RC clock. EN=1, standby mode Mode select Mode select RAM read and write control signal. 1 => can not read and write. 0=> can read and write. RAM data select signal 1=> RAM Data, 0=>Address RAM write signal, low write RAM read signal, low read RAM data or address bus LCD load signal between one COMMON signal to another. MAIN=1, the master unit will output LOAD signal. MAIN=0, the slave will accept the signal from master unit. Coupling capacitor Coupling capacitor Reference voltage input, highest V1K lowest V5 LCD waveform output
VSS4 VSS3 VSS2+ VSS2VREG MAIN
Power Power Power Power Power I
EN
I
M1 M0 RAMEN RAMADS RAMW RAMR RAMD3~RAM D0 LOAD
I I
I/O
CA CB V1~V5 O1~O80
I I I O
* This specification are subject to be changed without notice.
9.14.2001
5
EM83040B LCD CONTROLLER
ary relimin P
FUNCTION DESCRIPTIONS
(1)User can use MAIN pin to chose master unit or slave unit. MAIN 1 Unit MASTER Function Generate these signals: Load, CA, CB, VSS2+, VSS2-, VSS3, VSS4, VOUT Internal RC clock Accept these Master unit signals Load, VOUT, V1, V2, V3, V4, V5 No internal RC clock
0
SLAVE
(2)User can use M1,M2 to choose four modes. As followed MASTER MAIN M1 M0 Segment Mode1 1 0 0 O(16:1)=S(16:1) Mode2 1 0 1 Mode3 1 1 0 O(32:1)=S(32:1) Mode4 1 1 1 O(48:1)=S(48:1) SLAVE MAIN M1 M0 Segment Mode1 0 0 0 O(80:1)=S(80:1) Mode2 0 0 1 O(80:1)=S(80:1) Mode3 0 1 0 O(80:1)=S(80:1) Mode4 0 1 1 O(80:1)=S(80:1) * S=Segment, C=Common * (M1, M0) for Master must same as Slave unit (3)RAM control Write mode Common O(80:17)=C(64:1) O(80:1)=C(80:1) O(80:33)=C(48:1) O(80:49)=C(32:1) Common BIAS 1/9 1/9 1/7 1/5 BIAS 1/9 1/9 1/7 1/5
FIG. 3 LCD RAM can be written or read with control signal. The RAMEN pin can select a RAM which can be read or write. The RAMADS pin can select whether * This specification are subject to be changed without notice. 9.14.2001
6
EM83040B LCD CONTROLLER
ar y relimin P
RAMD(3:0) are data or address of RAM. At the address mode, RAMADS is low and user should sent address three times, from address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data mode, user can sent one or more nibble data which address can be increased by internal counter. Once the RAMEN pin is high, the RAM can not read and write. (4)Read control
Ten
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address (11:8) A2=address(7:4) A1=address(3:0) ADDRESS A3 A2 A1 RAM enable RAM disable
DATA D1 D2
Tdd
D3
Tdh Tdv
FIG. 4 As same as write mode, user has to sent address three times. And read data from RAM one by one which address can be increased by internal counter. Note!! Be sure to make RAMR low pulse 2uS (Tdv +data) width and 2uS (Tdd) high width at least. (5) RAM mapping RAM address is from 0 to address 2562 User fill "1" to LCD RAM, LCD driver will generate "light" waveform. Otherwise, it will generate a "dark" waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user can refer to fig.5 and Table 1 to get the idea of LCD ram mapping. The other RAM can use as general RAM for data storage if not mapping to LCD display. And the RAM of address 2560, 2561 and 2562 is control registers. Table 1: LCD mapping RAM area Common Segment 32 48 32 80 48 32 48 80 64 16 64 80 80 0 80 80 Any Any
Master/slave Master Slave Master Slave Master Slave Master Slave Any
Display area 1,2,3 1,2,3,4 1,2,5,6 1,2,3,4,5,6,7 1,5,8 1,2,3,4,5,6,7,8,9 No mapping RAM 1,2,3,4,5,6,7,8,9,10 Area 11 is general RAM
* This specification are subject to be changed without notice.
9.14.2001
7
EM83040B LCD CONTROLLER
ary relimin P
Address 2560,2561 2562 Control register
Address 2560,2561,2562 Control register
address2559 ...................
address2547 ......................................................................................................................... address2528
COM80
Area 11
EMPTY AREA
LCD RAM
Area 10
COM64
address2047 ................... : : : :
address2035 ......................................................................................address2019...............address2016
Area 9 Area 7
: :
: :
Area 8 Area 5
COM48
address1535 ................... : :
address1523 ............................................................address1511........................................address1504 :
Area 6
:
address1023 ................... : :
address1011 .......................address1003 ............................................................................. address0992
COM32
Area 4
Area 3
:
Area 2
:
Area 1
COM2 COM1
address0063 ................... address0031 ...................
address0051 ................... ..................................... .......................... ................................... address0032 address0019 ................... address0011................ address7........... address0003............... address0000 b3 b2 b1 b0 ................... s80s79s78s77 s48 s32 s16 b3 b2 b1 b0 s4 s3 s2 s1
Fig.5
As same as write mode , user has to sent address three times. And read data from RAM one by one which address can be increased by internal counter. NOTE!! Be sure to make RAMR low pulse 2 S (Tdv+data) width and 2 S (Tdd) high width at least. (5) RAM mapping RAM address is from 0 to address 2559 User fill "1" to LCD RAM , LCD driver will generate "light" waveform. Otherwise , it will generate a "dark" waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user can refer to fig.5 to get the idea of LCD ram mapping. The other RAM can use as general RAM for data storage. And the RAM of address 2560 is a control register.
* This specification are subject to be changed without notice.
9.14.2001
8
EM83040B LCD CONTROLLER
ar y relimin P
(6) LCD waveform
frame V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND dark V1 V2 V3 V4 V5 GND light
com0
com1
com2
seg
seg
Fig.6
* This specification are subject to be changed without notice.
9.14.2001
9
EM83040B LCD CONTROLLER
(7) Control register
ary relimin P
Address Bit3 Bit2 Bit1 Bit0 2560 IRS IR2 IR1 IR0 2561 REG3 REG2 REG1 REG0 2562 PS1 PS0 REG5 REG4 X: don't care Default status of Address 2560,2561 and 2562, respectively: 0010, 0000, 0000 Address 2562 bit3~2(PS1, PS0) be selected: Use settings PS1 PS0 Step-up circuit X V regulator circuit O O V/F circuit External voltage input
Only the internal power supply is used Only the V regulator circuit and the V/F circuit are used Only the V/F circuit is used Only the external power supply is used
1 1
1 0
O O
X VOUT
0 0
1 0
X X
X X
O X
V1 V1 to V5
Address 2562 bit1~0 and 2561 bit3~0 (Reg5~Reg0) is selected the VEV value REG5~REG0 000000 000001 011111 100000 111110 111111 VEV 1.2 V 1.212 V 1.572 V 1.584 V 1.944 V 1.956 V
VOUT
VEV step
0.012V
V1
Rb
V EV
VREG
Ra
Fig.7 * This specification are subject to be changed without notice. 9.14.2001
10
EM83040B LCD CONTROLLER
Address 2560 bit3 (IRS) is internal resistor selected IRS=0: internal regulator resistor is used. IRS=1: internal regulator resistor is not used. (External resistor is used) Address 2560 bit0~2(IR2, IR1, IR0) is selected for the V1 voltage regulator internal resistance ratio IR2~IR0 Resistor ratio (1+Rb/Ra) 000 3.0 001 3.5 010 4.0 011 4.5 100 5.0 101 5.5 110 6.0 111 6.5 The V1 voltage can be calculated using equation A over the range where VDD < V1 VOUT V1=(1+Rb/Ra) * VEV *(94%~97%) (Equation A) (94%~97%) depend on loading Example: Default: IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 0), and (REG5~0)=(000000) V1=(1+Rb/Ra) * VEV*(94%~97%)=4.0 * 1.2*(94%~97%)= 4.51 V~4.65V When IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 1), and (REG5~0)=(100000) V1=(1+Rb/Ra) * VEV*(94%~97%)=4.5 * 1.584*(94%~97%)= 6.7~6.91 V FIG. 8 show the V1 voltage measured by values of the internal resistance ratio resistor (1+Rb/Ra) for V1 voltage adjustment and electric volume resister (REG5~REG0). FIG. 8 The output voltage V1 is determined by function of the V1 voltage regulator ratio register (1+Rb/Ra), and the electric volume resister (REG5~REG0). (8) The step-up voltage circuit Case of the double step-up, the triple step-up and Case of the quad step-up VOUT is output voltage pin the bias voltage V1 is supported from VREG. (a) Double step-up, (b) Triple step-up, (c) Quad step-up (d) five times step-up C1=0.47 to 1.0gf, C2=1.0 to 4.7uf
VOUT VSS4 VSS3 CB CA
C2
ar y relimin P
VOUT VSS4 VSS3 CB
C2 C2
VOUT VSS4
C2
VOUT VSS4 VSS3
C2 C2 C2
VSS3 CB CA
C2
CB
C2
CA
CA
C2
EM83040B
EM83040B
EM83040B
EM83040B
VSS2+ VSS2VREG V1 V2 V3 V4 V5
C1
C2
VSS2+ VSS2VREG V1 V2 V3 V4 V5
VSS2+
C2
VSS2+
C2
C2
VSS2VREG
VSS2VREG V1 V2 V3 V4 V5
C1
V1 V2 V3 V4 V5
C1
C1
(a) VOUT=2*VDD
(b) VOUT=3*VDD
(c) VOUT=4*VDD FIG. 9
(d) VOUT=5*VDD 9.14.2001
11
* This specification are subject to be changed without notice.
EM83040B LCD CONTROLLER
ary relimin P
(9) Reference circuit examples are as following FIG. 10 (a) Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,0) (b) Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,1) When internal regulator resistor is not used (external resistor is used), V1=VREG*(1+Rb'/Ra') (c) Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,0) (d) Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,1), When internal regulator resistor is not used (external resistor is used), V1=VREG*(1+Rb'/Ra') (e) Only the V/F circuit is used, control register (PS1, PS0)=(0,1) (f) Only the external power supply is used, control register (PS1, PS0)=(0,0)
VDD
VOUT MAIN VSS4 VSS3 CB
C2 C2 C2
VDD
VOUT MAIN VSS4 VSS3 CB
C2 C2 C2
VDD
VOUT MAIN VSS4 VSS3 CB CA
EXTERNAL POWER SUPPLY
CA
CA
EM83040B
EM83040B
EM83040B
VSS2+
C2
VSS2+
C2
VSS2+ VSS2VREG V1 V2 V3 V4 V5
VSS2VREG V1 V2 V3 V4 V5
C1
VSS2VREG V1 V2 V3 V4 V5
C1 Ra' Rb'
C1
(a)
(b)
(c)
VDD
VOUT VSS4 VSS3 CB CA
EXTERNAL POWER SUPPLY
VDD
VOUT VSS4 VSS3 CB CA
VDD
VOUT VSS4 VSS3 CA CB
EM83040B
EM83040B
VSS2+ VSS2VREG V1 V2 V3 V4 V5
C1 Ra' Rb'
VSS2+ VSS2VREG V1 V2 V3 V4 V5
C1 EXTERNAL POWER SUPPLY
EM83040B
VSS2+ VSS2VREG V1 V2 V3 V4 V5
EXTERNAL POWER SUPPLY
(d)
(e) FIG. 10
(f)
* This specification are subject to be changed without notice.
9.14.2001
12
EM83040B LCD CONTROLLER
ar y relimin P
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE STEP-UP VOLTAGE
VDD Vin Ta VOUT
<3.5 -0.5 TO Vdd 0.5 -30 TO 80 <18
V V C V
DC ELECTRICAL CHARACTERISTICS (TA= -30C ~ 80C, VDD=3V5%, VSS=0V)
Parameter Input voltage Sym. Min. VDD 2.5 2.5 2.5 Output Low current Standby current Operating voltage IOL ISD IOP 2.5 -100 1 180 Typ. Max. 5.5 5.5 4.0 3.3 4 220 A A A V Unit Condition With double step-up With triple step-up With quad step-up With five times step-up VDD=3V EN=1 EN=0, MAIN =1(MASTER) , DC converter enable, Five times step-up (M1, M0)=(1,1) V1=11V, 250KHz clock, No load EN=0 . MAIN =0 (SLAVE) ,DC converter enable, Five times step-up (M1, M0)=(1,1) V1=11V, 250KHz clock, No load Current of a buffer
40
70
A
Current of a buffer (V1 toV5) Voltage variation of regulator Regulator current BIAS resister
Ibuf 4 Vreg V-0.1 Ireg R_bias 1800
6 10 V V+0.1 10 15 2000 2200
A V A k
AC ELECTRICAL CHARACTERISTICS (TA= -30C ~ 80C, VDD=3V VSS=0V)
Parameter RC clock variable Frame period Load period Enable time Write low pulse Data hold time Data to data time Data valid time Sym. Vrc Tframe Tload Ten Tw Tdh Tdd Tdv Min. -20 1/64 31 30 2 500 2 1500 Typ. Max. +20 Unit % S S S S nS S nS
* This specification are subject to be changed without notice.
9.14.2001
13
EM83040B LCD CONTROLLER
AC TIMING
LCD control timing
ary relimin P
EN Tframe FRAME LOAD C0 C1 Tload CM C0 POSITIVE FRAME NEGATIVE FRAME
S0
S1
S2
S3
SN
Fig .11 LCD control timing
Ten RAM enable RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address(11:8) A2=address(7:4) A1=address(3:0) ADDRESS A3 A2 Tdh Tw A1 D1 Tdd D2 DATA D3
RAM disable
Fig .12 LCD RAM write mode
* This specification are subject to be changed without notice.
9.14.2001
14
EM83040B LCD CONTROLLER
ar y relimin P
Ten RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address (11:8) A2=address(7:0) A1=address(3:0) D1= first nibble D2=second nibble D3=third nibble data ADDRESS A3 A2 A1 DATA D1 Tdv Tdh D2 Tdd D3 RAM enable RAM disable
Fig .13 LCD RAM read mode
APPLICATION CIRCUIT
(1) C32 x S48
VDD VDD VDD
VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0)
LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
NC
NC
Fig .14 * This specification are subject to be changed without notice. 9.14.2001
15
EM83040B LCD CONTROLLER
(2) C32 x S128
C31 : : C0
ary relimin P
LCD 32*128
S127 ...... S80 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT VSS VDD VDD VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0)
S79 ...... S0 LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT NC NC NC NC NC NC NC CONNECT TO MASTER CHIP
VDD VDD VDD
NC
MASTER
SLAVE
Fig .15 (3) C48 x S112
C47 : : C0 S111 ...... S80 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
LCD 48*112
S79 ...... S0 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT NC NC NC NC NC NC NC CONNECT TO MASTER CHIP
LOAD VOUT VSS VDD GND
VDD VDD GND
NC
MASTER
SLAVE
Fig .16 * This specification are subject to be changed without notice. 9.14.2001
16
EM83040B LCD CONTROLLER
(4) C64 x S96
ar y relimin P
C63 : : C0 S95 ...... S80 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5
LCD 64*96
S79 ...... S0 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT NC NC NC NC NC NC NC CONNECT TO MASTER CHIP
LOAD VOUT VSS GND GND
VDD GND GND
NC
MASTER
SLAVE
Fig .17
* This specification are subject to be changed without notice.
9.14.2001
17
EM83040B LCD CONTROLLER
ary relimin P
(5) C80 x S160
C79 : : C0
LCD 80*160
S79 ...... S0 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT VSS GND VDD VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT NC NC NC NC NC NC NC CONNECT TO MASTER CHIP
VDD GND GND
NC
MASTER
SLAVE1
S159 ...... S80 VDD GND MAIN M1 M0 EN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 CB CA VSS2+ VSS2VREG V1 V2 V3 V4 V5 LOAD VOUT NC NC NC NC NC NC NC CONNECT TO MASTER CHIP
VSS GND VDD
SLAVE2
Fig .18
* This specification are subject to be changed without notice.
9.14.2001
18
EM83040B LCD CONTROLLER
PAD DIAGRAM
OP_79_ OP_78_ OP_77_ OP_76_ OP_75_ OP_74_ OP_73_ OP_72_ OP_71_ OP_70_ OP_69_ MAIN ENB
ar y relimin P
OP_68_ OP_67_ OP_66_ OP_65_ OP_64_ OP_63_ OP_62_ OP_61_ OP_60_ OP_59_ OP_58_ OP_57_ OP_56_ OP_55_ OP_54_ OP_53_ OP_52_ OP_51_
M0
3
4 RAMENB RAMADS RAMW RAMR RAMD_3_ RAMD_2_ RAMD_1_ RAMD_0_ LOAD VDD GND VOUT VSS4 VSS3 CB CA VSS2A VSS2B VV1 V2 VREG 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 35
M1
2
1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 94 93 92 91 90 89 88 87 86 85 84
OP_50_ OP_49_ OP_48_ OP_47_ OP_46_ OP_45_ OP_44_ OP_43_ OP_42_ OP_41_ OP_40_ OP_39_ OP_38_ OP_37_ OP_36_ OP_35_ OP_34_ OP_33_ OP_32_ OP_31_ OP_30_
(0,0)
83 82 81 80 79 78 77 76 75 74
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
OP_0_
OP_1_
OP_2_
OP_3_
OP_4_
OP_5_
OP_6_
OP_7_
OP_8_
OP_9_
OP_10_
OP_11_
OP_12_
OP_13_
OP_14_
OP_15_
OP_16_
OP_17_
OP_18_
OP_19_
OP_20_
OP_21_
OP_22_
OP_23_
OP_24_
OP_25_
OP_26_
OP_27_
OP_28_
Chip Size : 3890 m x 2500 m Pad No. Sym. 1 MAIN 2 M1 3 M0 4 ENB(EN) 5 6 7 8 9 RAMENB(RAMEN) 10 RAMADS 11 RAMW 12 RAMR 13 RAMD_3_ 14 RAMD_2_ 15 RAMD_1_ 16 RAMD_0_ 17 LOAD 18 VDD 20 GND * This specification are subject to be changed without notice. X -1370.0 -1480.0 -1590.0 -1700.0 Y 1120.0 1120.0 1120.0 1120.0
-1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0
1065.0 955.0 845.0 735.0 630.0 525.0 420.0 315.0 210.0 105.0 0.0 9.14.2001
OP_29_
V3
V4
V5
19
EM83040B LCD CONTROLLER
ary relimin P
Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Sym. VSS4 VSS3 CB CA VSS2A(VSS2+) VSS2B(VSS2-) VV1(V1) V2 VREG X -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 Y -210.0 -315.0 -420.0 -525.0 -630.0 -735.0 -845.0 -955.0 -1065.0
V3 V4 V5 OP_0_ OP_1_ OP_2_ OP_3_ OP_4_ OP_5_ OP_6_ OP_7_ OP_8_ OP_9_ OP_10_ OP_11_ OP_12_ OP_13_ OP_14_ OP_15_ OP_16_ OP_17_ OP_18_ OP_19_ OP_20_ OP_21_ OP_22_ OP_23_ OP_24_ OP_25_ OP_26_ OP_27_
-1700.0 -1590.0 -1480.0 -1370.0 -1265.0 -1160.0 -1055.0 -950.0 -845.0 -740.0 -635.0 -530.0 -425.0 -320.0 -215.0 -110.0 -5.0 100.0 205.0 310.0 415.0 520.0 625.0 730.0 835.0 940.0 1045.0 1150.0 1255.0 1365.0 1475.0
-1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 9.14.2001
20
* This specification are subject to be changed without notice.
EM83040B LCD CONTROLLER
ar y relimin P
Pad No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Sym. OP_28_ OP_29_ X 1585.0 1695.0 Y -1120.0 -1120.0
OP_30_ OP_31_ OP_32_ OP_33_ OP_34_ OP_35_ OP_36_ OP_37_ OP_38_ OP_39_ OP_40_ OP_41_ OP_42_ OP_43_ OP_44_ OP_45_ OP_46_ OP_47_ OP_48_ OP_49_ OP_50_
1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1660.0
-1065.0 -955.0 -845.0 -735.0 -630.0 -525.0 -420.0 -315.0 -210.0 -105.0 0.0 105.0 210.0 315.0 420.0 525.0 630.0 740.0 850.0 960.0 1115.0
OP_51_ OP_52_ OP_53_ OP_54_ OP_55_ OP_56_ OP_57_ OP_58_ OP_59_ OP_60_
1695.0 1585.0 1475.0 1365.0 1255.0 1150.0 1045.0 940.0 835.0 730.0
1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 9.14.2001
21
* This specification are subject to be changed without notice.
EM83040B LCD CONTROLLER
ary relimin P
Pad No. 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Sym. OP_61_ OP_62_ OP_63_ OP_64_ OP_65_ OP_66_ OP_67_ OP_68_ OP_69_ OP_70_ OP_71_ OP_72_ OP_73_ OP_74_ OP_75_ OP_76_ OP_77_ OP_78_ OP_79_ X 625.0 520.0 415.0 310.0 205.0 100.0 -5.0 -110.0 -215.0 -320.0 -425.0 -530.0 -635.0 -740.0 -845.0 -950.0 -1055.0 -1160.0 -1265.0 Y 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0
* The substrate must be fixed at GND level or floating, cannot fixed to VDD level.
* This specification are subject to be changed without notice.
9.14.2001
22

▲Up To Search▲

Price & Availability of EM83040B

	To Download EM83040B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .